The present disclosure relates to a memory control apparatus, a memory system, an information processing system, and a memory control method. Specifically, the present disclosure relates to a memory control apparatus, a memory system, an information processing system, and a memory control method for controlling a memory having an upper limit for the number of writes.
In an information processing system in recent years, a non-volatile memory is sometimes used as an auxiliary storage apparatus or a storage. Generally, memory cells that constitute a non-volatile memory deteriorate over time and are worn out due to data writing. When the number of writes reaches a certain count, an error occurrence rate exceeds a tolerance, and the product life of the memory cells is ended.
In a non-volatile memory having a lifetime, when writes are concentrated on a specific address, the memory cell corresponding to the address is consumed, and the life thereof is ended more quickly than others, with the result that the number of memory cells which are incapable of being used may be increased. In view of this, in the non-volatile memory, a leveling process for degrees of consumption of the memory cells is often performed. The process is called as a wear leveling process.
In the wear leveling process, a memory controller has been proposed which records the number of data writes for each address in a flash memory, and an address to which a write is less frequently performed is preferentially set as a write target (see, for example, Japanese Patent No. 4863749). If the degree of consumption of the memory cell caused by one write is assumed to be constant, an address to which the write is less frequently performed has a smaller degree of consumption and thus has a longer remaining life. Therefore, by preferentially writing data to an address to which the write is less frequently performed, the degrees of consumption of the memory cells are leveled.